Eliminating Useless Messages in Write-Update Protocols on Scalable Multiprocessors

Cache coherence protocols for shared-memory multiprocessors use invalidations or updates to maintain coherence across processors. Although invalidation protocols usually produce higher miss rates, update protocols typically perform worse. Detailed simulations of these two classes of protocol show that the excessive network traac caused by update protocols signiicantly degrades performance , even with innnite bandwidth. Motivated by this observation, we categorize the coherence traac in update-based protocols and show that, for most applications, more than 90% of all updates generated by the protocol are unnecessary. We identify application characteristics that generate useless update traac, and compare the isolated and combined eeects of several software and hardware techniques for eliminating useless updates. These techniques include dynamic and static hybrid protocols , software caching, and coalescing write buuers. Our simulations show that software caching (where data layout and coherence are managed under programmer or compiler control) and the dynamic hybrid protocol reduce useless updates the most, but coalescing write buuers produce fewer, albeit larger, coherence messages. As a result, coalescing write buuers usually produce the best running time, except when the block size is large or the bandwidth is limited. Finally, based on the observation that the techniques we consider are unable to eliminate a large number of useless updates, we suggest directions for further reducing the useless traac in update-based protocols.